1. Field of the Invention
The present invention relates to a memory cell and more particularly, to a memory cell that can be mounted on a substrate in a standard CMOS process and written with information electrically. In addition, the present invention relates to an erasing method of information recorded in the memory cell and a nonvolatile semiconductor memory device comprising the plurality of memory cells.
2. Description of the Related Art
Conventionally, there is provided a nonvolatile semiconductor memory device that can be provided in the standard CMOS process without adding a new process to the process and write information electrically (refer to Japanese Laid-Open Patent Publication No. 6-334190 (referred to as the patent document 1 hereinafter), for example). A constitution of a nonvolatile semiconductor memory device disclosed in the patent document 1 will be described with reference to FIG. 13. FIG. 13A is a schematic sectional view showing a memory cell provided in the nonvolatile semiconductor memory device disclosed in the patent document 1 and FIG. 13B is an equivalent circuit thereof.
According to a memory cell 100 shown in FIG. 13A, an N-type well 3 is formed on a P-type semiconductor substrate 2, and P-type impurity diffusion layers 11 and 12 and an N+ type impurity diffusion layer 13 are formed on the well 3. In addition, the P-type impurity diffusion layer 12 and the N+ type impurity diffusion layer 13 are separated by an element separating insulation film 32.
In addition, N-type impurity diffusion layers 9 and 10 are separately formed on the semiconductor substrate 2 in a region in which the N-type well 3 is not formed (referred to as the “region outside the well” occasionally hereinafter). In addition, the N-type impurity diffusion layer 10 and the P-type impurity diffusion layer 11 formed on the N-type well 3 are separated by an element separating insulation film 31.
In addition, a first gate electrode 7 is formed above the region outside the well through a first gate insulation film 5 so as to overlap with a region sandwiched by the N-type impurity diffusion layers 9 and 10. Meanwhile, a second gate electrode 6 is formed above the N-type well 3 through a second gate insulation film 4 so as to overlap with a region sandwiched by the P-type impurity diffusion layers 11 and 12. In addition, the first gate electrode 7 and the second gate electrode 6 are electrically connected through a conductor 8.
In addition, the memory cell 100 comprises a contact 21 electrically connected to the N-type impurity diffusion layer 9, a contact 22 electrically connected to the N-type impurity diffusion layer 10, and a contact 23 electrically connected to the P-type impurity diffusion layers 11 and 12 and the N+ type impurity diffusion layer 13. As shown in FIG. 13A, the P-type impurity diffusion layers 11 and 12 and the N+ type impurity diffusion layer 13 are connected to the same node and when a predetermined voltage is applied from the contact 23, the same voltage is applied uniformly to the diffusion layers 11, 12 and 13.
Thus, the nonvolatile semiconductor memory device having the conventional constitution is provided by comprising memory cell array in which the above memory cells 100 are arranged in a row direction and a column direction. At this time, the memory cells having predetermined positional relation are electrically connected by a plurality of bit lines, word lines, and source lines. In the following description, it is assumed that the contact 21, the contact 22 and the contact 23 are connected to the bit line, the source line, the word line, respectively.
That is, the memory cell 100 shown in FIG. 13A comprises a MOS transistor 40 including the P-type semiconductor substrate 2, the N-type impurity diffusion layer 9, the N-type impurity diffusion layer 10, the first gate insulation film 5 and the first gate electrode 7, and a MOS capacitor 41 including the N-type well 3, the P-type impurity diffusion layer 11, the P-type impurity diffusion layer 12, the second gate insulation film 4 and the second gate electrode 6. Thus, the first gate electrode 7 constituting the MOS transistor 40 and the second gate electrode 6 constituting the MOS capacitor 41 are connected through the conductor 8, and the first gate electrode 7 is electrically insulated from the semiconductor substrate 2 and the N-type impurity diffusion layers 9 and 10 by the first gate insulation film 5, and the second gate electrode 6 is electrically insulated from the N-type well 3 and the P-type impurity diffusion layers 11 and 12 by the first gate insulation film 4, whereby the first gate electrode 7 and the second gate electrode 6 (and the conductor 8 electrically connecting them) constitute a floating gate electrode FG (refer to FIG. 13B).
In the memory cell 100 constituted as described above, it is assumed that a predetermined first positive voltage is applied to the N-type impurity diffusion layer 9 through the contact 21, the ground voltage is applied to the N-type impurity diffusion layer 10 through the contact 22, and a predetermined second positive voltage higher than the first positive voltage is applied to the P-type impurity diffusion layers 11 and 12 and the N+ type impurity diffusion layer 13 through the contact 23 (this voltage applying condition is referred to as the “first voltage state” hereinafter). At this time, when the second positive voltage is sufficiently higher than the charged potential of the second gate electrode 6, in other words, when the potential of the second gate electrode 6 is sufficiently lower than the potentials of the N-type well 3 and the P-type impurity diffusion layers 11 and 12, an inversion layer is formed at the interface between the N-type well 3 and the second gate insulation film 4 under the second gate electrode 6 (referred to as the “capacitor side inversion layer” hereinafter). At this time, since a minority-carrier hole in the capacitor side inversion layer is supplied from the adjacent P-type impurity diffusion layers 11 and 12, the potential of the inversion layer is coupled to the second positive voltage.
Here, predetermined capacitance is provided between the capacitor side inversion layer and the second gate electrode 6 depending on a dimension and a material. Meanwhile, in the first gate electrode 7 electrically connected to the second gate electrode 6 also, when the potential of the first gate electrode is sufficiently higher than that of the semiconductor substrate 2 in the positive direction at the overlapping part of the first gate electrode 7 and the semiconductor substrate 2, an inversion layer is generated at the interface between the semiconductor substrate 2 and the first gate insulation film 5 (referred to as the “transistor side inversion layer” hereinafter) under the first gate electrode 7, so that predetermined capacitance is provided between the transistor side inversion layer and the first gate electrode 7 depending on a dimension and a material.
When it is assumed that the potential of the semiconductor substrate 2 is the ground potential in the above first voltage state, the potential difference of the second positive voltage is generated between the semiconductor substrate 2 and the capacitor side inversion layer. Since the second gate electrode 6 and the first gate electrode 7 are electrically connected and have the same potential, the second gate electrode 6 and the first gate electrode 7 (that is, the floating gate electrode FG) have a predetermined positive potential determined by the capacitance with the capacitor side inversion layer and the capacitance with the transistor side inversion layer (potential is increased).
At this time, when the potential of the first gate electrode 7 becomes higher than the semiconductor substrate 2 and its potential difference is sufficiently high, the transistor side inversion layer is formed at the interface between the overlapping part of the first gate electrode 7 and the semiconductor substrate 2, and the first gate insulation film 6 as described above. In the above first voltage state, the first positive voltage is applied to the N-type impurity diffusion layer 9 through the contact 21 and the ground voltage is applied to the N-type impurity diffusion layer 10 through the contact 22, so that the positive electric field is generated from the N-type impurity diffusion layer 10 to the N-type impurity diffusion layer 9 and the electrons in the N-type impurity diffusion layer 10 are accelerated by that electric field and become hot electrons. This hot electron is drawn to the high voltage state of the first gate electrode 7 and as a result, injected in the floating gate electrode FG. Thus, the floating gate electrode FG is negatively charged.
In the MOS transistor 40, the voltage value to be applied to the N-type well 3 through the contact 23 to form the transistor side inversion layer varies depending on the amount of the electrons accumulated in the floating gate electrode FG. That is, in a case where a predetermined third positive voltage is applied through the contact 23 and a predetermined fourth positive voltage is applied to the N-type impurity diffusion layer 9 through the contact 21, when the transistor side inversion layer is formed and the MOS transistor 40 becomes conductive, the electrons are not sufficiently accumulated in the floating gate electrode FG. Meanwhile, when the transistor side inversion layer is not formed and the MOS transistor 40 is in the nonconductive state, it means that the electrons are sufficiently accumulated in the floating gate electrode FG. In general, the case where the floating gate electrode FG accumulates electrons sufficiently and negatively charged is a programmed state and the reverse case is a non-programmed state.
That is, the information of the memory cell 100 is read by applying the fourth positive voltage to the N-type impurity diffusion layer 9 through the contact 21, applying the ground voltage to the N-type impurity diffusion layer 10 through the contact 22, and applying the third positive voltage to each of the P-type impurity diffusion layers 11 and 12 and the N+ type impurity diffusion layer 13 through the contact 23 (this voltage applying condition is referred to as the “second voltage state” hereinafter) to determine whether a current flowing in the bit line connected to the contact 21 or a current flowing in the source line connected to the contact 22 is detected or not and relate the determined result to two values 0 and 1.
As described above, the information is programmed by setting the first voltage state to the memory cell 100 and the information is read by setting the second voltage state to it. In addition, since the floating gate electrode FG that is negatively charged when the hot electron is injected in the programming process is surrounded by the insulation films (first gate insulation film 4 and the second gate insulation film 5), the charge is not volatile, so that the charged state can be maintained for a long period of time. In addition, since the programming process or the reading process on the memory cell 100 is selected by the voltage applied from the contact 23, the P-type impurity diffusion layers 11 and 12 and the N+ type impurity diffusion layer 13 receiving the voltage from the contact 23 corresponds to the control gate electrode (referred to as the control gate electrode CG (not shown in the drawing) hereinafter) when the memory cell 100 is regarded as one memory cell in the nonvolatile semiconductor memory device.
Next, a description will be made of a case where the floating gate electrode FG is negatively charged and information stored in the memory cell 100 is erased.
When the erasing action is performed, the ground voltage is applied to the P-type impurity diffusion layers 11 and 12 and the N+ type impurity diffusion layer 13 through the contact 23, a predetermined fifth positive voltage (the same as the first positive voltage or more) is applied to the N-type impurity diffusion layer 9 through the contact 21, and the contact 22 is set in the floating (high-impedance) state (this voltage applying condition is referred to as the “third voltage state” hereinafter). At this time, a potential difference is generated between the floating gate electrode FG (first gate electrode 7) and the N-type impurity diffusion layer 9 and a high electric field is generated, so that electrons accumulated in the floating gate electrode FG are withdrawn to the N-type impurity diffusion layer 9 by a FN (Fowler Nordheim) tunneling phenomenon, whereby the programmed state is canceled. In addition, in this case, the electrons may be withdrawn by applying the fifth positive voltage to the N-type impurity diffusion layer 10 through the contact 22 as well to generate a high electric field from the floating gate electrode FG to the surface of the opposed semiconductor substrate 2.
In addition, as another erasing method, a method in which a hot hole is injected to the floating gate electrode FG is disclosed (refer to Boaz Eitan et al., “Can NROM, a 2 Bit, Trapping Storage NVM Cell, Give a real Challenge to Floating Gate Cells?”, Extended Abstracts of the 1999 International Conference on Solid State Devices and Materials, Tokyo, 1999, p. 522-523, (referred to as the document 2 hereinafter), for example). The method disclosed in the above document is applied to the memory cell shown in FIG. 13 as follows. That is, a voltage from the ground potential through to the negative voltage is applied to the control gate electrode CG and a predetermined positive voltage is applied to the N-type impurity diffusion layer 9 through the contact 21. At this time, a high potential difference having an opposite polarity is generated between the N-type impurity diffusion layer 9 and the control gate electrode CG and as a result, the surface of the N-type impurity diffusion layer 9 becomes a deep deficiency sate and an energy band bends abruptly. At this time, the electrons tunnels from a valence band to a conductive band by the band-to-band tunneling. At this time, a pair of electron and hole is generated and the electron flows in the N-type impurity diffusion layer 9 and absorbed while the hole is accelerated in a horizontal direction by an electric field in the horizontal direction between the N-type impurity diffusion layer 9 and the semiconductor substrate 2 (assuming that the semiconductor substrate 2 is at the ground potential) and becomes a hot hole. Thus, the hot hole is drawn to the positive voltage state that is close to the ground potential of the first gate electrode 7 and then injected to the floating gate electrode FG (band-to-band tunneling induced hot hole injection). The electron accumulated in the floating gate electrode FG is offset with the hot hole and the negatively charged state is canceled, whereby information is erased.
In addition, although the erasing method using the FN tunneling phenomenon and the erasing method using the hot hole injection are similar in the voltage applying method, they are different in that the former method needs to use an extremely thin gate insulation film to increase the inner electric field of the insulation film sufficiently to the degree that the tunneling phenomenon is generated within a practically applicable voltage range, while the latter method does not need to use the extremely thin gate insulation film.
According to the erasing method disclosed in the above document 1, the high electric field is generated between the floating gate electrode FG and the N-type impurity diffusion layer 9 by generating the high potential difference between the control gate electrode CG and the N-type impurity diffusion layer 9, and the electrons accumulated in the floating gate electrode FG are withdrawn by the high electric field, whereby the information is erased. That is, as the potential difference between the control gate electrode CG and the N-type impurity diffusion layer 9 is increased, the erasing ability can be enhanced. Here, as a method to increase the potential difference, a first method to lower the voltage applied from the contact 23 (to a negative voltage) and a second method to raise the voltage applied from the contact 21 (to a positive high voltage) are considered.
However, when the first method is used, that is, when the negative voltage is applied from the contact 23, the junction between the N-type well 3 to which the negative voltage is applied and the P-type semiconductor substrate 2 is in the forward direction and both show conductive state, so that the original function of the memory cell, that is, to store information could not be implemented. In addition, in the case of the second method is used, that is, in the case where the voltage applied from the contact 21 is increased, when the voltage is increased to the degree that erasing ability can be provided, it exceeds the withstand voltage of the N-type impurity diffusion layer 9 in some cases. In this case, the diffusion layer 9 could be destroyed and the original function of the memory cell, that is, to store information could not be implemented. That is, the applicable voltage value from the contact 21 is limited by the withstand voltage of the N-type impurity diffusion layer 9. Conversely, in order to increase the withstand voltage of the N-type impurity diffusion layer 9, it is necessary to correct an impurity density distribution of the N-type impurity diffusion layer 9, so that it is difficult to implement the above process in the standard CMOS manufacturing process without adding a new step.
Therefore, when the voltage value within a range not exceeding the withstand voltage of the N-type impurity diffusion layer 9 is applied from the contact 21, in order to provide the erasing ability efficiently (in order to sufficiently increase the inner electric field of the insulation film to the degree that the tunneling phenomenon is generated within the practically applicable voltage range), there is a method of thinning the thickness of the first gate insulation film 5 in order to increase the electric field between the floating gate electrode FG (first gate electrode 7) and the N-type impurity diffusion layer 9. However, in this method, the electrons accumulated in the floating gate electrode FG after the programming process could escape through the thin insulation film (corresponding to the above-described extremely thin gate insulation film) even though the erasing action is not performed (electric charge retention reliability is lowered).
In addition, according to the method disclosed in the above document 2, since it is necessary to apply the negative voltage from the contact 23 to generate the hot hole, it cannot be employed in the memory cell comprising the constitution shown in FIG. 13 for the same reason as the above.